Memory Hardware Support for Sparse Computations

Address computations and indirect, hence double, memory accesses in sparse matrix application software render sparse computations to be ine cient in general. In this paper we propose memory architectures that support the storage of sparse vectors and matrices. In a rst design, called vector storage, a matrix is handled as an array of sparse vectors, stored as singly-linked lists. Deletion and insertion of a vector is done rowor column-wise only. In a second design, called matrix storage, a higher level of sophistication is achieved. A sparse matrix is stored as a bi-directionally threaded doubly-linked list of elements. This approach enables both rowand column-wise operations. Reading a row (column) can be done at the speed of one element (real value and indices) per memory cycle, while extracting or updating takes 2 memory cycles. Inserting an element can be done once every 2.5 memory cycles. A pipelined variant with 3-fold interleaved memory and write bu ers yields higher e ciency, close to one sparse matrix element per memory cycle for all basic vector operations. In-memory operations also decrease the burden on processor, cache, and bus. 4